TABLE 3-3: CORE REGISTER MAP
SFR Name
Address
(Home)
Bit 15
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7
W0
0000
W1
0002
W2
0004
W3
0006
W4
0008
W5
000A
W6
000C
W7
000E
W8
0010
W9
0012
W10
0014
W11
0016
W12
0018
W13
001A
W14
001C
W15
001E
SPLIM
0020
ACCAL
0022
ACCAH
0024
ACCAU
0026
ACCBL
0028
ACCBH
002A
ACCBU
002C
PCL
002E
PCH
0030
—
TBLPAG
0032
—
PSVPAG
0034
—
RCOUNT
0036
DCOUNT
0038
DOSTARTL 003A
DOSTARTH 003C
—
DOENDL
003E
W0/WREG
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
SPLIM
ACCAL
ACCAH
Sign Extension (ACCA<39>)
ACCBL
ACCBH
Sign Extension (ACCB<39>)
PCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RCOUNT
DCOUNT
DOSTARTL
—
—
—
—
—
—
—
—
DOENDL
DOENDH
SR
Legend:
Note:
0040
—
—
—
—
—
—
—
—
—
0042
OA
OB
SA
SB
OAB SAB
DA
DC
IPL2
u = uninitialized bit; — = unimplemented bit, read as ‘0’
Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Bit 6
IPL1
Bit 5
IPL0
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
Reset State
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 1000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
ACCAU
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
ACCBU
0000 0000 0000 0000
0000 0000 0000 0000
PCH
0000 0000 0000 0000
TBLPAG
0000 0000 0000 0000
PSVPAG
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
0 uuuu uuuu uuuu uuu0
DOSTARTH
0000 0000 0uuu uuuu
0 uuuu uuuu uuuu uuu0
DOENDH
0000 0000 0uuu uuuu
RA
N
OV
Z
C 0000 0000 0000 0000