ST7PLITEU09M3TR View Datasheet(PDF) - STMicroelectronics
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ST7PLITEU09M3TR Datasheet PDF : 115 Pages
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ST7LITEU05 ST7LITEU09
POWER SAVING MODES (Cont’d)
9.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the LTCSR/ATCSR reg-
ister status as shown in the following table:.
LTCSR
TBIE bit
ATCSR
OVFIE
bit
ATCSR
CK1 bit
ATCSR
CK0 bit
Meaning
0
x
x
0
0
0
x
x
ACTIVE-HALT
mode disabled
0
1
1
1
1
x
x
x ACTIVE-HALT
x
1
0
1 mode enabled
9.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when active halt mode is enabled.
The MCU can exit ACTIVE-HALT mode on recep-
tion of a Lite Timer / AT Timer interrupt or a RE-
SET.
– When exiting ACTIVE-HALT mode by means of
a RESET, a 256 or 512 CPU cycle delay occurs.
After the start up delay, the CPU resumes oper-
ation by fetching the reset vector which woke it
up (see Figure 26).
– When exiting ACTIVE-HALT mode by means of
an interrupt, the CPU immediately resumes oper-
ation by servicing the interrupt vector which woke
it up (see Figure 26).
When entering ACTIVE-HALT mode, the I bit in
the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and the selected timer counter (LT/AT) are running
to keep a wake-up time base. All other peripherals
are not clocked except those which get their clock
supply from another clock generator (such as ex-
ternal or auxiliary oscillator).
Caution: As soon as ACTIVE-HALT is enabled,
executing a HALT instruction while the Watchdog
is active does not generate a RESET if the
WDGHALT bit is reset.
This means that the device cannot spend more
than a defined delay in this power saving mode.
Figure 25. ACTIVE-HALT Timing Overview
RUN
ACTIVE
HALT
256 OR 512 CPU
CYCLE DELAY 1)
RUN
HALT
INSTRUCTION
[Active Halt Enabled]
RESET
OR
INTERRUPT
FETCH
VECTOR
Figure 26. ACTIVE-HALT Mode Flow-chart
HALT INSTRUCTION
(Active Halt enabled)
OSCILLATOR ON
PERIPHERALS 2) OFF
CPU
OFF
I BIT
0
N
RESET
N
Y
INTERRUPT 3)
Y
OSCILLATOR ON
PERIPHERALS 2) OFF
CPU
ON
I BIT
X 4)
256 OR 512 CPU CLOCK
CYCLE DELAY
OSCILLATOR ON
PERIPHERALS ON
CPU
ON
I BITS
X 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripherals clocked with an external clock
source can still be active.
3. Only the Lite Timer RTC and AT Timer interrupts
can exit the MCU from ACTIVE-HALT mode.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
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