ST7PLITEU09M3TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7PLITEU09M3TR

8-bit MCU with single voltage Flash memory, ADC, timers

STMicroelectronics 

ST7LITEU05 ST7LITEU09

POWER SAVING MODES (Cont’d)

9.4.2 HALT MODE

The HALT mode is the lowest power consumption

mode of the MCU. It is entered by executing the

‘HALT’ instruction when active halt mode is disa-

bled.

The MCU can exit HALT mode on reception of ei-

ther a specific interrupt (see Table 10, “Interrupt

mapping,” on page 32) or a RESET. When exiting

HALT mode by means of a RESET or an interrupt,

the main oscillator is immediately turned on and

the 256 or 512 CPU cycle delay is used to stabilize

it. After the start up delay, the CPU resumes oper-

ation by servicing the interrupt or by fetching the

reset vector which woke it up (see Figure 28).

When entering HALT mode, the I bit in the CC reg-

ister is forced to 0 to enable interrupts. Therefore,

if an interrupt is pending, the MCU wakes immedi-

ately.

In HALT mode, the main oscillator is turned off

causing all internal processing to be stopped, in-

cluding the operation of the on-chip peripherals.

All peripherals are not clocked except the ones

which get their clock supply from another clock

generator (such as an external or auxiliary oscilla-

tor).

The compatibility of Watchdog operation with

HALT mode is configured by the “WDGHALT” op-

tion bit of the option byte. The HALT instruction

when executed while the Watchdog system is en-

abled, can generate a Watchdog RESET (see sec-

tion 15.1 on page 105 for more details).

Figure 27. HALT Timing Overview

RUN

HALT

256 OR 512

CPU CYCLE DELAY

RUN

RESET

OR

HALT

INTERRUPT

INSTRUCTION

[Active Halt disabled]

FETCH

VECTOR

Figure 28. HALT Mode Flow-chart

HALT INSTRUCTION

(Active Halt disabled)

ENABLE

WATCHDOG

WDGHALT 1)

0

DISABLE

1

WATCHDOG

RESET

OSCILLATOR OFF

PERIPHERALS 2) OFF

CPU

OFF

I BIT

0

N

RESET

N

Y

INTERRUPT 3)

Y

OSCILLATOR ON

PERIPHERALS OFF

CPU

ON

I BIT

X 4)

256 OR 512 CPU CLOCK

CYCLE DELAY 5)

OSCILLATOR ON

PERIPHERALS ON

CPU

ON

I BITS

X 4)

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Notes:

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

2. Peripheral clocked with an external clock source

can still be active.

3. Only some specific interrupts can exit the MCU

from HALT mode (such as external interrupt). Re-

fer to Table 10, “Interrupt mapping,” on page 32 for

more details.

4. Before servicing an interrupt, the CC register is

pushed on the stack. The I bit of the CC register is

set during the interrupt routine and cleared when

the CC register is popped.

5. The CPU clock must be switched to 1MHz

(RC/8) or AWU RC before entering HALT mode.

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