dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 2
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 1
IC1IE: Input Capture Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0
INT0IE: External Interrupt 0 Flag Status bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 105