DSPIC33FJ32GP802-I/SP View Datasheet(PDF) - Microchip Technology
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DSPIC33FJ32GP802-I/SP Datasheet PDF : 402 Pages
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dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
14.0 INPUT CAPTURE
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04,
and
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 12. Input Capture”
(DS70198) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able from the Microchip website
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 devices support
up to four input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
1. Simple Capture Event modes:
- Capture timer value on every falling edge of
input at ICx pin
- Capture timer value on every rising edge of
input at ICx pin
2. Capture timer value on every edge (rising and
falling)
3. Prescaler Capture Event modes:
- Capture timer value on every 4th rising edge
of input at ICx pin
- Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select one of two 16-
bit timers (Timer2 or Timer3) for the time base. The
selected timer can use either an internal or external
clock.
Other operational features include:
• Device wake-up from capture pin during CPU
Sleep and Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
- Interrupt optionally generated after 1, 2, 3 or
4 buffer locations are filled
• Use of input capture to provide additional sources
of external interrupts
Note:
Only IC1 and IC2 can trigger a DMA data
transfer. If DMA data transfers are
required, the FIFO buffer size must be set
to ‘1’ (ICI<1:0> = 00)
FIGURE 14-1:
INPUT CAPTURE BLOCK DIAGRAM
ICM<2:0>
Prescaler Mode
(16th Rising Edge)
101
ICx pin
Prescaler Mode
(4th Rising Edge)
Rising Edge Mode
TMR2 TMR3
100
ICTMR
011 CaptureEvent
FIFO CONTROL
To CPU
Falling Edge Mode
010
ICxBUF
FIFO
Edge Detection
Mode
001
Sleep/Idle
Wake-up Mode
ICI<1:0>
/N
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
ICM<2:0>
Set Flag ICxIF
(In IFSx Register)
001
111
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 195
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