CY8C26643 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

CY8C26643

8-Bit Programmable System-on-Chip (PSoC™) Microcontrollers

Cypress Semiconductor 

Interrupts

8.6 GPIO Interrupt

GPIO Interrupts are polarity configurable and pin-wise

maskable (within each Port’s pin configuration registers).

They all share the same interrupt priority and vector.

Any general purpose I/O can be used as an interrupt

source. The GPIO bit in the General Interrupt Mask Reg-

ister (INT_MSK0) must be set to enable pin interrupts, as

well as the enable bits for each pin, which are located in

the Port x Interrupt Enable Registers (PRTxIE). There

are user selectable options to generate an interrupt on 1)

any change from the last read state, 2) rising edge, and

3) falling edge.

When Interrupt on Change is selected, the state of the

GPIO pin is stored when the port is read. Changes from

this state will then assert the interrupt, if enabled.

GPIO Cell

All GPIO INTOUTs

“1”

OR

R

D

Q IRQ

To Priority

Decode Logic

PIN

Int Logic

INTOUTn

GPIO Int Enable

BIT S, INT_MSK0

GPIO BIT IE

PORTX IE Register

(PRT0IE...PRT5IE)

Figure 11: GPIO Interrupt Enable Diagram

For a GPIO interrupt to occur, the following steps must

be taken:

1. The pin Drive Mode must be set so the pin can be

an input.

2. The pin must be enabled to generate an interrupt by

setting the appropriate bit in the Port interrupt

Enable Register (PRTxIE).

6. Because the GPIO interrupts all share the same

interrupt vector, the source for the GPIO interrupt

must be cleared before any other GPIO interrupt will

occur (i.e., the OR gate in FigureTitle 11 “ors” all of

the INTOUTn signals together). If any of the

INTOUTn signals are high, the flip-flop in FigureTitle

11 will not see a rising edge and no IRQ will occur.

3. The edge type for the interrupt must be set in the

Port Interrupt Control 0 and Control 1 Registers

(PRTxIC0 and PRTxIC1). Edge type must be set to

a value other than 00.

4. The GPIO bit must be set in the General Interrupt

Mask Register (INT_MSK0).

5. The Global Interrupt Enable bit must be set.

September 5, 2002

Document #: 38-12010 CY Rev. ** CMS Rev. 3.20

47

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