QL7180-6PS484C View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL7180-6PS484C

Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

EclipsePlus Family Data Sheet Rev. A

Figure 12: RAM Cell Synchronous Write Timing

WCLK

WA

tSWA

tHWA

WD

tSWD

tHWD

WE

tSWE

tHWE

RD

old data

new data

tWCRD

Table 9: RAM Cell Synchronous & Asynchronous Read Timing

Symbol

Parameter

tSRA

tHRA

tSRE

tHRE

tRCRD

rPDRD

RAM Cell Synchronous Read Timing

RA setup time to RCLK: time the READ ADDRESS must be stable before the active

edge of the READ CLOCK

RA hold time to RCLK: time the READ ADDRESS must be stable after the active

edge of the READ CLOCK

RE setup time to WCLK: time the READ ENABLE must be stable before the active

edge of the READ CLOCK

RE hold time to WCLK: time the READ ENABLE must be stable after the active

edge of the READ CLOCK

RCLK to RD: time between the active READ CLOCK edge and the time when the

data is available at RD

RAM Cell Asynchronous Read Timing

RA to RD: time between when the READ ADDRESS is input and when the DATA

is output

Value (ns)

Min.

Max.

0.686 ns

-

0 ns

-

0.243 ns

-

0 ns

-

-

2.225 ns

-

2.405 ns

© 2006 QuickLogic Corporation

www.quicklogic.com

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