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QL7180-6PS484C View Datasheet(PDF) - QuickLogic Corporation

Part Name
Description
Manufacturer
QL7180-6PS484C
QuickLogic
QuickLogic Corporation 
QL7180-6PS484C Datasheet PDF : 65 Pages
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EclipsePlus Family Data Sheet Rev. A
Figure 15: EclipsePlus Input Register Cell
QE
D
R
tISU
+
-
tSID
PAD
Symbol
tISU
tIHL
tICO
tIRST
tIESU
tIEH
Table 10: Input Register Cell
Parameter
Input register setup time: the time the synchronous input of the pin must be stable
before the active clock edge
Input register hold time: the time the synchronous input of the flip-flop must be
stable after the active clock edge
Input register clock-to-out: the time taken by the flip-flop to output after the active
clock edge
Input register reset delay: the time between when the flip-flop is “reset” (low) and
when the output is consequently “reset” (low)
Input register clock enable setup time: the time “enable” must be stable before
the active clock edge
Input register clock enable hold time: the time “enable” must be stable after the
active clock edge
Value (ns)
Min.
Max.
3.308 ns 3.526 ns
0 ns
-
-
0.494 ns
-
0.464 ns
0.830 ns 0.987 ns
0 ns
-
© 2006 QuickLogic Corporation
www.quicklogic.com
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