ST72334J4TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72334J4TC

8-bit MCU for automotive with single voltage Flash/ROM memory, ADC, 16-bit timers, SPI, SCI interfaces

STMicroelectronics 

ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto

8.2 RESET SEQUENCE MANAGER (RSM)

8.2.1 Introduction

The reset sequence manager includes three RE-

SET sources as shown in Figure 14:

■ External RESET source pulse

■ Internal LVD RESET (Low Voltage Detection)

■ Internal WATCHDOG RESET

These sources act on the RESET pin and it is al-

ways kept low during the delay phase.

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of three

phases as shown in Figure 13:

■ Delay depending on the RESET source

■ 4096 CPU clock cycle delay

■ RESET vector fetch

Figure 14. Reset Block Diagram

The 4096 CPU clock cycle delay allows the oscil-

lator to stabilise and ensures that recovery has

taken place from the Reset state.

The RESET vector fetch phase duration is 2 clock

cycles.

Figure 13. RESET Sequence Phases

DELAY

RESET

INTERNAL RESET FETCH

4096 CLOCK CYCLES VECTOR

RESET

VDD

RON

fCPU

INTERNAL

RESET

WATCHDOG RESET

LVD RESET

28/150

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