ST72334J4TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72334J4TC

8-bit MCU for automotive with single voltage Flash/ROM memory, ADC, 16-bit timers, SPI, SCI interfaces

STMicroelectronics 

ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto

WATCHDOG TIMER (Cont’d)

The application program must write in the CR reg-

ister at regular intervals during normal operation to

prevent an MCU reset. The value to be stored in

the CR register must be between FFh and C0h

(see Table 12 .Watchdog Timing (fCPU = 8 MHz)):

– The WDGA bit is set (watchdog enabled)

– The T6 bit is set to prevent generating an imme-

diate reset

– The T[5:0] bits contain the number of increments

which represents the time delay before the

watchdog produces a reset.

Table 12.Watchdog Timing (fCPU = 8 MHz)

CR Register

initial value

WDG timeout period

(ms)

Max

FFh

98.304

Min

C0h

1.536

13.1.7 Register Description

CONTROL REGISTER (CR)

Read / Write

Reset Value: 0111 1111 (7Fh)

7

0

WDGA T6 T5 T4 T3 T2 T1 T0

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Note: This bit is not used if the hardware watch-

dog option is enabled by option byte.

Notes: Following a reset, the watchdog is disa-

bled. Once activated it cannot be disabled, except

by a reset.

The T6 bit can be used to generate a software re-

set (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction

will generate a Reset.

13.1.4 Hardware Watchdog Option

If Hardware Watchdog is selected by option byte,

the watchdog is always active and the WDGA bit in

the CR is not used.

Refer to the device-specific Option Byte descrip-

tion.

13.1.5 Low Power Modes

Mode

WAIT

HALT

Description

No effect on Watchdog.

Immediate reset generation as soon as the

HALT instruction is executed if the Watch-

dog is activated (WDGA bit is set).

13.1.6 Interrupts

None.

Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB).

These bits contain the decremented value. A reset

is produced when it rolls over from 40h to 3Fh (T6

becomes cleared).

STATUS REGISTER (SR)

Read / Write

Reset Value*: 0000 0000 (00 h)

7

-

-----

0

- WDOGF

Bit 0 = WDOGF Watchdog flag.

This bit is set by a watchdog reset and cleared by

software or a power on/off reset. This bit is useful

for distinguishing power/on off or external reset

and watchdog reset.

0: No Watchdog reset occurred

1: Watchdog reset occurred

* Only by software and power on/off reset

Note: This register is not used in versions without

LVD Reset.

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