QL8025-6PV100C View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL8025-6PV100C

Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

(FOLSVH,, )DPLO\ 'DWD 6KHHW 5HY %

$& &KDUDFWHULVWLFV

The AC Specifications (at VCC = 1.8 V, TA = 25° C, Worst Case Corner,

Speed Grade = -7 (K = 1.16)) are provided from 7DEOH  to 7DEOH . Logic Cell diagrams and

waveforms are provided from )LJXUH  to )LJXUH .

)LJXUH  (FOLSVH,, Logic Cell

7DEOH  /RJLF &HOOV

6\PERO

3DUDPHWHU

/RJLF &HOOV

tPD

Combinatorial Delay of the longest path: time taken by the combinatorial circuit to

output

tSU

Setup time: time the synchronous input of the flip-flop must be stable before the

active clock edge

tHL

Hold time: time the synchronous input of the flip-flop must be stable after the active

clock edge

tCO

Clock-to-out delay: the amount of time taken by the flip-flop to output after the

active clock edge.

tCWHI

tCWLO

tSET

Clock High Time: required minimum time the clock stays high

Clock Low Time: required minimum time that the clock stays low

Set Delay: time between when the flip-flop is ”set” (high)

and when the output is consequently “set” (high)

tRESET

Reset Delay: time between when the flip-flop is ”reset” (low) and when the output

is consequently “reset” (low)

tSW

Set Width: time that the SET signal must remain high/low

tRW

Reset Width: time that the RESET signal must remain high/low

9DOXH

0LQ

0D[

-

0.257 ns

0.22 ns

-

0 ns

-

-

0.46 ns

0.46 ns

-

0.255 ns

-

-

0.18 ns

-

0.3 ns

0.3 ns

0.09 ns

-

-



‡‡‡‡‡‡ ZZZTXLFNORJLFFRP

Preliminary ‹  4XLFN/RJLF &RUSRUDWLRQ

Share Link: