QL8025-6PV100C View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL8025-6PV100C

Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

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tIRST

Input register reset delay: time between when the flip-flop is “reset”(low) and when

the output is consequently “reset” (low)

- 0.99 ns

tIESU

Input register clock enable setup time: time “enable” must be stable before the

active clock edge

0.37 ns

-

tIEH

Input register clock enable hold time: time “enable” must be stable after the active

clock edge

0 ns

-

R

CLK

D

tISU

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Q

tIC O

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