EP3C5E324A8ES View Datasheet(PDF) - Altera Corporation

Part Name

Description

Manufacturer

EP3C5E324A8ES

Cyclone III Device Handbook

Altera Corporation 

3–8

Chapter 3: Memory Blocks in the Cyclone III Device Family

Memory Modes

1 Violating the setup or hold time on the M9K memory block input registers may

corrupt memory contents. This applies to both read and write operations.

Single-Port Mode

Single-port mode supports non-simultaneous read and write operations from a single

address. Figure 3–7 shows the single-port memory configuration for Cyclone III

device family M9K memory blocks.

Figure 3–7. Single-Port Memory (1), (2)

data[ ]

address[ ]

wren

byteena[]

addressstall

inclock

inclocken

rden

aclr

q[]

outclock

outclocken

Notes to Figure 3–7:

(1) You can implement two single-port memory blocks in a single M9K block.

(2) For more information, refer to “Packed Mode Support” on page 3–5.

During a write operation, the behavior of the RAM outputs is configurable. If you

activate rden during a write operation, the RAM outputs show either the new data

being written or the old data at that address. If you perform a write operation with

rden deactivated, the RAM outputs retain the values they held during the most recent

active rden signal.

To choose the desired behavior, set the Read-During-Write option to either New Data

or Old Data in the RAM MegaWizard Plug-In Manager in the Quartus II software. For

more information about read-during-write mode, refer to “Read-During-Write

Operations” on page 3–15.

The port width configurations for M9K blocks in single-port mode are as follow:

■ 8192 × 1

■ 4096 × 2

■ 2048 × 4

■ 1024 × 8

■ 1024 × 9

■ 512 × 16

■ 512 × 18

■ 256 × 32

■ 256 × 36

Cyclone III Device Handbook

Volume 1

December 2011 Altera Corporation

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