EP3C5E324A8ES View Datasheet(PDF) - Altera Corporation
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EP3C5E324A8ES Datasheet PDF : 274 Pages
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Chapter 3: Memory Blocks in the Cyclone III Device Family
Memory Modes
3–13
Figure 3–13 shows the Cyclone III device family M9K memory block in the shift
register mode.
Figure 3–13. Cyclone III Device Family Shift Register Mode Configuration
w × m × n Shift Register
m-Bit Shift Register
W
W
m-Bit Shift Register
W
W
m-Bit Shift Register
W
m-Bit Shift Register
W
n Number of Taps
W
W
ROM Mode
Cyclone III device family M9K memory blocks support ROM mode. A .mif initializes
the ROM contents of these blocks. The address lines of the ROM are registered. The
outputs can be registered or unregistered. The ROM read operation is identical to the
read operation in the single-port RAM configuration.
FIFO Buffer Mode
Cyclone III device family M9K memory blocks support single-clock or dual-clock
FIFO buffers. Dual clock FIFO buffers are useful when transferring data from one
clock domain to another clock domain. Cyclone III device family M9K memory blocks
do not support simultaneous read and write from an empty FIFO buffer.
f For more information about FIFO buffers, refer to the SCFIFO and DCFIFO
Megafunctions user guide.
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
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