ST7PLIT115BF1M3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7PLIT115BF1M3

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI

STMicroelectronics 

ST7LITE1xB

13.3.3 Operating Conditions with Low Voltage Detector (LVD)

13.3.3.1 Operating Conditions with LVD at TA = -40 to 125°C, unless otherwise specified

Symbol

Parameter

Conditions

Min Typ Max Unit

VIT+(LVD)

Reset release threshold

(VDD rise)

VIT-(LVD)

Reset generation threshold

(VDD fall)

High Threshold

Med. Threshold

Low Threshold

High Threshold

Med. Threshold

Low Threshold

3.80 4.20 4.60

3.20 3.55 3.90

2.65 2.85 3.10

V

3.70 4.00 4.35

3.10 3.35 3.70

2.50 2.70 2.90

Vhys

VtPOR

tg(VDD)

IDD(LVD)

LVD voltage threshold hysteresis

VDD rise time rate 1)2)

Filtered glitch delay on VDD 1)

LVD/AVD current consumption

VIT+(LVD)-VIT-(LVD)

Not detected by the LVD

200

mV

100 ms/V

150

ns

200

µA

Notes:

1. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production.

2. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is rec-

ommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 106 on

page 136 and note 4.

113/159

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