ST7PLIT115BF1M3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST7PLIT115BF1M3
STMicroelectronics
ST7PLIT115BF1M3 Datasheet PDF : 159 Pages
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ST7LITE1xB
13.10 COMMUNICATION INTERFACE CHARACTERISTICS
13.10.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for VDD,
fOSC, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Symbol
Parameter
fSCK
1/tc(SCK)
SPI clock frequency
tr(SCK)
tf(SCK)
tsu(SS) 1)
th(SS) 1)
tw(SCKH) 1)
tw(SCKL) 1)
tsu(MI) 1)
tsu(SI) 1)
th(MI) 1)
th(SI) 1)
ta(SO) 1)
tdis(SO) 1)
tv(SO) 1)
th(SO) 1)
tv(MO) 1)
th(MO) 1)
SPI clock rise and fall time
SS setup time 4)
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Conditions
Master
fCPU=8MHz
Slave
fCPU=8MHz
Min
fCPU/128
0.0625
0
Max
fCPU/4
2
fCPU/2
4
Unit
MHz
see I/O port pin description
Slave
Slave
(4 x TCPU) + 50
120
Master
100
Slave
90
Master
100
Slave
100
Master
Slave
100
100
ns
Slave
0
120
Slave
240
120
Slave (after enable edge)
0
Master (after enable
120
edge)
0
Figure 107. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT
tsu(SS)
tc(SCK)
th(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
MISO OUTPUT
see note 2
tsu(SI)
tw(SCKH)
tw(SCKL)
tv(SO)
MSB OUT
th(SI)
BIT6 OUT
th(SO)
tr(SCK)
tf(SCK)
LSB OUT
tdis(SO)
see
note 2
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Notes:
1. Data based on design simulation, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
4. Depends on fCPU. For example, if fCPU=8MHz, then TCPU = 1/fCPU =125ns and tsu(SS)=550ns
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