ST7PLIT110BF0M3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7PLIT110BF0M3

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI

STMicroelectronics 

ST7LITE1xB

DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)

AUTORELOAD REGISTER (ATR1H)

Read / Write

Reset Value: 0000 0000 (00h)

15

8

0

0

0

0 ATR11 ATR10 ATR9 ATR8

AUTORELOAD REGISTER (ATR1L)

Read / Write

Reset Value: 0000 0000 (00h)

7

0

ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0

Bits 11:0 = ATR1[11:0] Autoreload Register 1.

This is a 12-bit register which is written by soft-

ware. The ATR1 register value is automatically

loaded into the upcounter CNTR1 when an over-

flow occurs. The register value is used to set the

PWM frequency.

PWM OUTPUT CONTROL REGISTER

(PWMCR)

Read/Write

Reset Value: 0000 0000 (00h)

7

0

0

OE3

0

OE2

0

OE1

0

OE0

Bits 7:0 = OE[3:0] PWMx output enable.

These bits are set and cleared by software and

cleared by hardware after a reset.

0: PWM mode disabled. PWMx Output Alternate

Function disabled (I/O pin free for general pur-

pose I/O)

1: PWM mode enabled

PWMx CONTROL STATUS REGISTER

(PWMxCSR)

Read / Write

Reset Value: 0000 0000 (00h)

7

0

0

0

0

0

OP_EN

OPEDG

E

OPx

CMPFx

Bits 7:4= Reserved, must be kept cleared.

Bit 3 = OP_EN One Pulse Mode Enable

This bit is read/write by software and cleared by

hardware after a reset. This bit enables the One

Pulse feature for PWM2 and PWM3. (Only availa-

ble for PWM3CSR)

0: One Pulse mode disabled for PWM2/3.

1: One Pulse mode enabled for PWM2/3.

Bit 2 = OPEDGE One Pulse Edge Selection.

This bit is read/write by software and cleared by

hardware after a reset. This bit selects the polarity

of the LTIC signal for One Pulse feature. This bit

will be effective only if OP_EN bit is set. (Only

available for PWM3CSR)

0: Falling edge of LTIC is selected.

1: Rising edge of LTIC is selected.

Bit 1 = OPx PWMx Output Polarity.

This bit is read/write by software and cleared by

hardware after a reset. This bit selects the polarity

of the PWM signal.

0: The PWM signal is not inverted.

1: The PWM signal is inverted.

Bit 0 = CMPFx PWMx Compare Flag.

This bit is set by hardware and cleared by software

by reading the PWMxCSR register. It indicates

that the upcounter value matches the Active DCRx

register value.

0: Upcounter value does not match DCRx value.

1: Upcounter value matches DCRx value.

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