ST7PLIT110BF0M3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7PLIT110BF0M3

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI

STMicroelectronics 

ST7LITE1xB

DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)

11.2.3.2 Dead Time Generation

A dead time can be inserted between PWM0 and

PWM1 using the DTGR register. This is required

for half-bridge driving where PWM signals must

not be overlapped. The non-overlapping PWM0/

PWM1 signals are generated through a program-

mable dead time by setting the DTE bit.

Dead time value = DT[6:0] x Tcounter1

DTGR[7:0] is buffered inside so as to avoid de-

forming the current PWM cycle. The DTGR effect

will take place only after an overflow.

Figure 40. Dead Time Generation

Tcounter1

Notes:

1. Dead time is generated only when DTE=1 and

DT[6:0] ≠ 0. If DTE is set and DT[6:0]=0, PWM out-

put signals will be at their reset state.

2. Half Bridge driving is possible only if polarities of

PWM0 and PWM1 are not inverted, i.e. if OP0 and

OP1 are not set. If polarity is inverted, overlapping

PWM0/PWM1 signals will be generated.

3. Dead Time generation does not work at 1 ms

timebase.

CK_CNTR1

CNTR1

PWM 0

PWM 1

DCR0 DCR0+1

counter = DCR0

OVF

ATR1

counter = DCR1

Tdt

PWM 0

Tdt

PWM 1

In the above example, when the DTE bit is set:

– PWM goes low at DCR0 match and goes high at

ATR1+Tdt

– PWM1 goes high at DCR0+Tdt and goes low at

ATR match.

Tdt = DT[6:0] x Tcounter1

With this programmable delay (Tdt), the PWM0

and PWM1 signals which are generated are not

overlapped.

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