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ST7PLIT110BF0M3 View Datasheet(PDF) - STMicroelectronics

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ST7PLIT110BF0M3 Datasheet PDF : 159 Pages
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ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
– At the second input capture on the falling edge of
the pulse, we assume that the values in the reg-
isters are as follows:
LTICR = LT2
ATICRH = ATH2
ATICRL = ATL2
Hence ATICR2 [11:0] = ATH2 & ATL2
Now pulse width P between first capture and sec-
ond capture will be:
P = decimal (F9 – LT1 + LT2 + 1) * 0.004ms + dec-
imal ((FFF * N) + N + ATICR2 - ATICR1 – 1) * 1ms
where N = No of overflows of 12-bit CNTR1.
Figure 46. Long Range Input Capture Timing Diagram
fOSC/32
TB Counter1 F9h 00h LT1
F9h 00h _ _ _ _ _ _ _ _ _ LT2 _ _ _ _ _ _
CNTR1
___
ATH1 & ATL1
___
ATH2 & ATL2
LTIC
LTICR
00h
LT1
LT2
ATICRH
0h
ATH1
ATH2
ATICRL
00h
ATL1
ATL2
ATICR = ATICRH[3:0] & ATICRL[7:0]
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