ST7LITE1xB
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.3.7 Force Update
In order not to wait for the counterx overflow to
load the value into active DCRx registers, a pro-
grammable counterx overflow is provided. For
both counters, a separate bit is provided which
when set, make the counters start with the over-
flow value, i.e. FFFh. After overflow, the counters
start counting from their respective auto reload
register values.
These bits are FORCE1 and FORCE2 in the
ATCSR2 register. FORCE1 is used to force an
overflow on Counter 1 and, FORCE2 is used for
Counter 2. These bits are set by software and re-
Figure 50. Force Overflow Timing Diagram
set by hardware after the respective counter over-
flow event has occurred.
This feature can be used at any time. All related
features such as PWM generation, Output Com-
pare, Input Capture, One-pulse (refer to Figure 15.
Dynamic DCR2/3 update in One Pulse Mode) can
be used this way.
fCNTRx
FORCEx
CNTRx
E03 E04
FFF
ATRx
FORCE2 FORCE1
ATCSR2 Register
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