M41ST84W
Figure 7. Bus timing requirements sequence
Operating modes
SDA
tBUF
SCL
P
tHD:STA
tR
tF
tHIGH
S
tLOW
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
SR
tSU:STO
P
AI00589
Table 2. AC characteristics
Symbol
Parameter(1)
Min
Max
Unit
fSCL
SCL clock frequency
0
400
kHz
tBUF
Time the bus must be free before a new transmission can
start
1.3
µs
tF
tHD:DAT(2)
tHD:STA
SDA and SCL fall time
Data hold time
START condition hold time
(after this period the first clock pulse is generated)
300
ns
0
µs
600
ns
tHIGH
tLOW
tR
tSU:DAT
tSU:STA
Clock high period
Clock low period
SDA and SCL rise time
Data setup time
START condition setup time
(only relevant for a repeated start condition)
600
ns
1.3
µs
300
ns
100
ns
600
ns
tSU:STO
STOP condition setup time
600
ns
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6 V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.
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