M41ST84W View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M41ST84W Datasheet PDF : 34 Pages
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Operating modes
M41ST84W
2.3
WRITE mode
In this mode the master transmitter transmits to the M41ST84W slave receiver. Bus protocol
is shown in Figure 11. Following the START condition and slave address, a logic '0' (R/W=0)
is placed on the bus and indicates to the addressed device that word address An will follow
and is to be written to the on-chip address pointer. The data word to be written to the
memory is strobed in next and the internal address pointer is incremented to the next
memory location within the RAM on the reception of an acknowledge clock. The M41ST84W
slave receiver will send an acknowledge clock to the master transmitter after it has received
the slave address (see Figure 8 on page 14) and again after it has received the word
address and each data byte.
2.4
Data retention mode
With valid VCC applied, the M41ST84W can be accessed as described above with READ or
WRITE cycles. Should the supply voltage decay, the M41ST84W will automatically deselect,
write protecting itself when VCC falls between VPFD(max) and VPFD(min). This is
accomplished by internally inhibiting access to the clock registers. At this time, the Reset pin
(RST) is driven active and will remain active until VCC returns to nominal levels. When VCC
falls below the battery backup switchover voltage (VSO), power input is switched from the
VCC pin to the external battery, and the clock registers and SRAM are maintained from the
attached battery supply.
All outputs become high impedance. On power up, when VCC returns to a nominal value,
write protection continues for trec. The RST signal also remains active during this time (see
Figure 18 on page 30).
For a further more detailed review of lifetime calculations, please see application note
AN1012.
Figure 11. WRITE mode sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
WORD
ADDRESS (An)
BUS ACTIVITY:
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+X P
AI00591
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