DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC33EV64GM102-I/SO
Microchip Technology
DSPIC33EV64GM102-I/SO Datasheet PDF : 500 Pages
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dsPIC33EVXXXGM00X/10X FAMILY
Figure 8-2 illustrates the DMA Controller block diagram.
FIGURE 8-2:
DMA CONTROLLER BLOCK DIAGRAM
SRAM
Arbiter
Peripheral Indirect Address
DMA Controller
DMA
Channels
01 2 3
DMA
Ready
Peripheral 1
CPU DMA
DMA X-Bus
CPU Peripheral X-Bus
IRQ to DMA
and Interrupt
Controller
Modules
CPU
Non-DMA
Peripheral
CPU DMA
DMA
Ready
Peripheral 2
CPU DMA
DMA
Ready
Peripheral 3
IRQ to DMA and
Interrupt Controller
Modules
IRQ to DMA and
Interrupt Controller
Modules
Note: CPU and DMA address buses are not shown for clarity.
8.1 DMAC Controller Registers
Each DMAC Channel x (where x = 0 to 3) contains the
following registers:
• 16-Bit DMA Channel x Control Register (DMAxCON)
• 16-Bit DMA Channel x IRQ Select Register
(DMAxREQ)
• 32-Bit DMA Channel x Start Address Register A
High/Low (DMAxSTAH/L)
• 32-Bit DMA Channel x Start Address Register B
High/Low (DMAxSTBH/L)
• 16-Bit DMA Channel x Peripheral Address
Register (DMAxPAD)
• 14-Bit DMA Channel x Transfer Count Register
(DMAxCNT)
Additional status registers (DMAPWC, DMARQC,
DMAPPS, DMALCA and DSADRH/L) are common to
all DMAC channels. These status registers provide
information on write and request collisions, as well as
on last address and channel access information.
The DMA Interrupt Flags (DMAxIF) are located in an
IFSx register in the interrupt controller. The
corresponding DMA Interrupt Enable bits (DMAxIE)
are located in an IECx register in the interrupt
controller and the corresponding DMA Interrupt
Priority bits (DMAxIP) are located in an IPCx register
in the interrupt controller.
2013-2016 Microchip Technology Inc.
DS70005144E-page 111
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