dsPIC33EVXXXGM00X/10X FAMILY
FIGURE 4-10:
EXTENDED DATA SPACE (EDS) WRITE ADDRESS GENERATION
EA<15> = 0
(DSWPAG = Don’t Care)
16-Bit DS EA
Byte
Select
Generate
No EDS Access 0
EA
PSV Address
EA<15>
1
EA
DSWPAG<8:0>
9 Bits
15 Bits
24-Bit EDS EA
Note: DS read access when DSRPAG = 0x000 will force an address error trap.
Byte
Select
The paged memory scheme provides access to
multiple 32-Kbyte windows in the EDS and PSV
memory. The Data Space Page registers, DSxPAG, in
combination with the upper half of the Data Space
address, can provide up to 16 Mbytes of additional
address space in the EDS and 8 Mbytes (DSRPAG
only) of PSV address space. The paged data memory
space is shown in Figure 4-11.
The Program Space (PS) can be accessed with a
DSRPAG of 0x200 or greater. Only reads from PS are
supported using the DSRPAG. Writes to PS are not
supported, therefore, the DSWPAG is dedicated to DS,
including EDS. The Data Space and EDS can be read
from and written to using DSRPAG and DSWPAG,
respectively.
2013-2016 Microchip Technology Inc.
DS70005144E-page 69