PIC18F46K80T-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F46K80T-I/SP

28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

Microchip Technology 

PIC18F66K80 FAMILY

10.5 RCON Register

The RCON register contains bits used to determine the

cause of the last Reset or wake-up from Idle or Sleep

modes. RCON also contains the bit that enables

interrupt priorities (IPEN).

REGISTER 10-19: RCON: RESET CONTROL REGISTER

R/W-0

R/W-1

R/W-1

R/W-1

R-1

IPEN

SBOREN

CM

RI

TO

bit 7

R-1

R/W-0

R/W-0

PD

POR

BOR

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

IPEN: Interrupt Priority Enable bit

1 = Enables priority levels on interrupts

0 = Disables priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6

SBOREN: Software BOR Enable bit

For details of bit operation, see Register 5-1.

bit 5

CM: Configuration Mismatch Flag bit

1 = A Configuration Mismatch Reset has not occurred

0 = A Configuration Mismatch Reset has occurred (must be subsequently set in software)

bit 4

RI: RESET Instruction Flag bit

For details of bit operation, see Register 5-1.

bit 3

TO: Watchdog Timer Time-out Flag bit

For details of bit operation, see Register 5-1.

bit 2

PD: Power-Down Detection Flag bit

For details of bit operation, see Register 5-1.

bit 1

POR: Power-on Reset Status bit

For details of bit operation, see Register 5-1.

bit 0

BOR: Brown-out Reset Status bit

For details of bit operation, see Register 5-1.

 2010-2012 Microchip Technology Inc.

DS39977F-page 167

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