PIC18F65K80T-I/SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F65K80T-I/SS

28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

Microchip Technology 

PIC18F66K80 FAMILY

REGISTER 27-59: TXBIE: TRANSMIT BUFFERS INTERRUPT ENABLE REGISTER(1)

U-0

—

bit 7

U-0

U-0

R/W-0

R/W-0

R/W-0

U-0

—

—

TXB2IE(2) TXB1IE(2) TXB0IE(2)

—

U-0

—

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-5

bit 4-2

bit 1-0

Unimplemented: Read as ‘0’

TXB2IE:TXB0IE: Transmit Buffer 2-0 Interrupt Enable bits(2)

1 = Transmit buffer interrupt is enabled

0 = Transmit buffer interrupt is disabled

Unimplemented: Read as ‘0’

Note 1: This register is available in Mode 1 and 2 only.

2: TXBnIE in PIE5 register must be set to get an interrupt.

REGISTER 27-60: BIE0: BUFFER INTERRUPT ENABLE REGISTER 0(1)

R/W-0

B5IE(2)

bit 7

R/W-0

B4IE(2)

R/W-0

B3IE(2)

R/W-0

B2IE(2)

R/W-0

B1IE(2)

R/W-0

B0IE(2)

R/W-0

RXB1IE(2)

R/W-0

RXB0IE(2)

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-2

bit 1-0

B<5:0>IE: Programmable Transmit/Receive Buffer 5-0 Interrupt Enable bits(2)

1 = Interrupt is enabled

0 = Interrupt is disabled

RXB<1:0>IE: Dedicated Receive Buffer 1-0 Interrupt Enable bits(2)

1 = Interrupt is enabled

0 = Interrupt is disabled

Note 1: This register is available in Mode 1 and 2 only.

2: Either TXBnIE or RXBnIE, in the PIE5 register, must be set to get an interrupt.

 2010-2012 Microchip Technology Inc.

DS39977F-page 437

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