PIC18F65K80T-I/SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F65K80T-I/SS

28/40/44/64-Pin, Enhanced Flash Microcontrollers with ECAN™ and nanoWatt XLP Technology

Microchip Technology 

PIC18F66K80 FAMILY

XORWF

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

Exclusive OR W with f

XORWF f {,d {,a}}

0  f  255

d  [0,1]

a  [0,1]

(W) .XOR. (f) dest

N, Z

0001 10da ffff ffff

Exclusive OR the contents of W with

register ‘f’. If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored back

in the register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 29.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

1

1

Q2

Read

register ‘f’

Q3

Process

Data

Q4

Write to

destination

Example:

XORWF

Before Instruction

REG

W

= AFh

= B5h

After Instruction

REG

W

= 1Ah

= B5h

REG, 1, 0

DS39977F-page 524

 2010-2012 Microchip Technology Inc.

Share Link: