ST72E632K2B0 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72E632K2B0
STMicroelectronics
ST72E632K2B0 Datasheet PDF : 109 Pages
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ST7263
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (DR)
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
These 3 bits, in conjunction with the SCP1 & SCP0
bits, define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
TR Dividing Factor SCT2 SCT1 SCT0
7
0
1
0
0
0
2
0
0
1
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
4
0
1
0
8
0
1
1
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 1).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 1).
BAUD RATE REGISTER (BRR)
Read/Write
Reset Value: 00xx xxxx (XXh)
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 & SCP0
bits, define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
RR Dividing Factor
1
SCR2
0
SCR1
0
SCR0
0
7
0
2
0
0
1
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
4
0
1
0
8
0
1
1
Bits 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
PR Prescaling Factor
SCP1
SCP0
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
1
0
0
3
0
1
4
1
0
13
1
1
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