ST72E632K2B0 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72E632K2B0

LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C

STMicroelectronics 

ST7263

USB INTERFACE (Cont’d)

5.6.4 Register Description

DMA ADDRESS REGISTER (DMAR)

Read / Write

Reset Value: Undefined

7

0

DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8

Bits 7:0=DA[15:8] DMA address bits 15-8.

Software must write the start address of the DMA

memory area whose most significant bits are given

by DA15-DA6. The remaining 6 address bits are

set by hardware. See the description of the IDR

register and Figure 2.

INTERRUPT/DMA REGISTER (IDR)

Read / Write

Reset Value: xxxx 0000 (x0h)

7

0

DA7 DA6 EP1 EP0 CNT3 CNT2 CNT1 CNT0

Bits 7:6 = DA[7:6] DMA address bits 7-6.

Software must reset these bits. See the descrip-

tion of the DMAR register and Figure 2.

Bits 5:4 = EP[1:0] Endpoint number (read-only).

These bits identify the endpoint which required at-

tention.

00: Endpoint 0

01: Endpoint 1

10: Endpoint 2

When a CTR interrupt occurs (see register ISTR)

the software should read the EP bits to identify the

endpoint which has sent or received a packet.

Figure 37. DMA Buffers

DA15-6,000000

Bits 3:0 = CNT[3:0] Byte count (read only).

This field shows how many data bytes have been

received during the last data reception.

Note: Not valid for data transmission.

101111

101000

100111

100000

011111

011000

010111

010000

001111

001000

000111

000000

Endpoint 2 TX

Endpoint 2 RX

Endpoint 1 TX

Endpoint 1 RX

Endpoint 0 TX

Endpoint 0 RX

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