ST72621L4M1(2002) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72621L4M1
(Rev.:2002)
(Rev.:2002)
STMicroelectronics
ST72621L4M1 Datasheet PDF : 133 Pages
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ST7262
12.12 10-BIT ADC CHARACTERISTICS
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ 1)
Max
Unit
fADC
VAIN
RAIN
CAIN
fAIN
ADC clock frequency
Conversion voltage range 2)
External input impedance
External capacitor on analog input
Variation frequency of analog input
signal
0.4
VSSA
4
VDDA
see
Figure 86
and
Figure
873)4)5)
MHz
V
kΩ
pF
Hz
CADC
tCONV
Internal sample and hold capacitor
Conversion time
fADC=4MHz
6
pF
28
µs
112
1/fADC
Figure 86. RAIN max. vs fADC with CAIN=0pF4)
Figure 87. Recommended CAIN/RAIN values5)
45
40
35
30
25
20
15
10
5
0
0
4 MHz
2 MHz
1 MHz
10
30
70
CPARASITIC (pF)
1000
100
10
1
0.1
0.01
Cain 10 nF
Cain 22 nF
Cain 47 nF
0.1
1
10
fAIN(KHz)
Figure 88. Typical Application with ADC
VDD
ST72XXX
VAIN
RAIN
AINx
CAIN
VT
0.6V
VT
0.6V
2kΩ(max)
10-Bit A/D
Conversion
IL
±1µA
CADC
6pF
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.
2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
5. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization and to allow
the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤ 4MHz.
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