ST7262
OPERATING CONDITIONS (Cont’d)
Figure 55. fCPU Versus VDD for low voltage devices
fCPU [MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
8
FUNCTIONALITY
GUARANTEED
IN THIS AREA
(UNLESS OTHERWISE
SPECIFIED IN THE
4
TABLES OF
PARAMETRIC DATA)
2
0
2.5
3.0
3.5
4
4.5
5
5.5 SUPPLY VOLTAGE [V]
12.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for VDD, fCPU, and TA. Refer to Figure 15 on page 21.
Symbol
Parameter
Conditions
Min Typ 1) Max Unit
VIT+
VIT-
Vhyst
VtPOR
Low Voltage Reset Threshold (VDD rising)
Low Voltage Reset Threshold (VDD falling)
Hysteresis (VIT+ - VIT-)
VDD rise time rate 3)
VDD Max. Variation 50V/ms
VDD Max. Variation 50V/ms
3.6
3.45
120 2)
0.5
3.8
3.65
150 2)
3.95
3.8
180 2)
50
V
V
mV
V/ms
Notes:
1. Not tested, guaranteed by design.
2. Not tested in production, guaranteed by characterization.
3. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production.
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