PSD834F5A-15UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD834F5A-15UI Datasheet PDF : 128 Pages
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AC/DC parameters
PSD8XXFX
Figure 39. Input to output disable / enable
INPUT
tER
tEA
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
Table 48. CPLD combinatorial timing (5 V devices)
) Symbol
Parameter
-70
-90
-15
Conditions
Min Max Min Max Min Max
Fast
PT
Aloc
Turbo
off
Slew
rate
(1)
Unit
t(s CPLD input
duc tPD
pin/feedback to
CPLD combinatorial
ro output
20
25
32 + 2 + 10 – 2 ns
P tEA
CPLD input to CPLD
output enable
21
26
32
+ 10 – 2 ns
olete tER
CPLD input to CPLD
output disable
21
26
32
+ 10 – 2 ns
bs tARP
CPLD register clear
or preset delay
21
26
33
+ 10 – 2 ns
) - O tARPW
CPLD register clear
or preset pulse width
10
20
29
+ 10
ns
ct(s tARD
CPLD array delay
Any
macrocell
11
16
22 + 2
ns
du 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
Pro Table 49. CPLD combinatorial timing (3 V devices)
olete Symbol
Parameter
Conditions
-12
Min Max
-15
Min Max
-20
Min Max
PT
Aloc
Turbo
off
Slew
rate
(1)
Unit
bs CPLD input
OtPD
pin/feedback to
CPLD combinatorial
40
45
50 + 4 + 20 – 6 ns
output
tEA
CPLD input to CPLD
output enable
43
45
50
+ 20 – 6 ns
tER
CPLD input to CPLD
output disable
43
45
50
+ 20 – 6 ns
tARP
CPLD register clear
or preset delay
40
43
48
+ 20 – 6 ns
100/128
Doc ID 7833 Rev 7
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