PSD833F3A-20UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD833F3A-20UI Datasheet PDF : 128 Pages
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PSD8XXFX
AC/DC parameters
Table 56. READ timing (5 V devices) (continued)
Symbol
Parameter
Conditions
-70
Min Max
-90
Min Max
-15
Turbo
Min Max off
Unit
tTHEH
tELTL
tAVPV
R/W setup time to Enable
R/W hold time After Enable
Address input valid to
Address output delay
6
10
18
ns
0
0
0
ns
(5)
20
25
30
ns
1. Any input used to select an internal PSD function.
2. RD timing has the same timing as DS, LDS, and UDS signals.
3. RD and PSEN have the same timing.
) 4. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
t(s 5. In multiplexed mode, latched addresses generated from ADIO delay to address output on any port.
duc Table 57.
Pro Symbol
READ timing (3 V devices)
Parameter
Conditions
-12
Min Max
-15
Min Max
-20
Min Max
Turbo
off
Unit
lete tLVLX
ALE or AS pulse width
so tAVLX
Address setup time
(1)
b tLXAX
Address hold time
(1)
- O tAVQV Address valid to data valid
(1)
) tSLQV CS valid to data valid
t(s RD to data valid 8-bit bus
(2)
uc tRLQV RD or PSEN to data valid 8-bit bus,
(3)
d 8031, 80251
ro tRHQX RD data hold time
(4)
te P tRLRH RD pulse width
le tRHQZ RD to data high-Z
(4)
o tEHEL
E pulse width
ObstTHEH R/W setup time to enable
26
26
30
ns
9
10
12
ns
9
12
14
ns
120
150
200 + 20 ns
120
150
200
ns
35
35
40
ns
45
50
55
ns
0
0
0
ns
38
40
45
ns
38
40
45
ns
40
45
52
ns
15
18
20
ns
tELTL
R/W hold time after enable
0
0
0
ns
tAVPV
Address input valid to
address output delay
(5)
33
35
40
ns
1. Any input used to select an internal PSD function.
2. RD timing has the same timing as DS, LDS, and UDS signals.
3. RD and PSEN have the same timing for 8031.
4. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
5. In multiplexed mode latched address generated from ADIO delay to address output on any port.
Doc ID 7833 Rev 7
107/128
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