PSD833F3A-20UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD833F3A-20UI Datasheet PDF : 128 Pages
| |||
PSD8XXFX
AC/DC parameters
Table 58.
Symbol
WRITE timing (5 V devices) (continued)
Parameter
Conditions
-70
-90
-15
Unit
Min Max Min Max Min Max
tWHPV
Trailing edge of WR to port output
valid using I/O port data register
(2)
27
30
38 ns
tDVMV
Data valid to port output valid
using macrocell register
Preset/Clear
(2)(4)
42
55
65 ns
tAVPV
Address input valid to address
output delay
(5)
20
25
30 ns
t(s) tWLMV
WR valid to port output valid using
macrocell register Preset/Clear
(2)(6)
48
55
65 ns
c 1. Any input used to select an internal PSD function.
u 2. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
rod 3. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
4. Assuming WRITE is active before data becomes valid.
P 5. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
te 6. Assuming data is stable before active WRITE signal.
sole Table 59. WRITE timing (3 V devices)
- Ob Symbol
Parameter
t(s) tLVLX
uc tAVLX
d tLXAX
Pro tAVWL
lete tSLWL
o tDVWH
bstWHDX
OtWLWH
ALE or AS pulse width
Address setup time
Address hold time
Address valid to Leading
Edge of WR
CS valid to Leading Edge of WR
WR data setup time
WR data hold time
WR pulse width
Conditions
-12
-15
-20
Unit
Min Max Min Max Min Max
26
26
30
(1)
9
10
12
ns
(1)
9
12
14
ns
(1)(2)
17
20
25
ns
(2)
17
20
25
ns
(2)
45
45
50
ns
(2)
7
8
10
ns
(2)
46
48
53
ns
tWHAX1 Trailing edge of WR to address invalid
(2)
10
12
17
ns
tWHAX2
Trailing edge of WR to DPLD address
invalid
(2)(3)
0
0
0
ns
tWHPV
Trailing edge of WR to port output
valid using I/O port data register
(2)
33
35
40 ns
tDVMV
Data valid to port output valid
using macrocell register Preset/Clear
(2)(4)
70
70
80 ns
Doc ID 7833 Rev 7
109/128
Share Link: 