PSD834F5A-15UI View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD834F5A-15UI

Flash in-system programmable (ISP) ipherals for 8-bit MCUs, 5 V

STMicroelectronics 

Power management

Figure 32. Enable Power-down flowchart

RESET

Enable APD

Set PMMR0 Bit 1 = 1

PSD8XXFX

OPTIONAL

Disable desired inputs to PLD

by setting PMMR0 bits 4 and 5

and PMMR2 bits 2 through 6.

t(s) No

ALE/AS idle

c for 15 CLKIN

u clocks?

rod Yes

P PSD in Power

te Down Mode

AI02892

bsole 17.4 PLD power management

- O The power and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in PMMR0. By

) setting the bit to '1,' the Turbo mode is off and the PLDs consume the specified standby

t(s current when the inputs are not switching for an extended time of 70ns. The propagation

delay time is increased by 10ns after the Turbo Bit is set to '1' (turned off) when the inputs

uc change at a composite frequency of less than 15 MHz. When the Turbo Bit is reset to '0'

d (turned on), the PLDs run at full power and speed. The Turbo Bit affects the PLD’s DC

ro power, AC power, and propagation delay.

P Blocking MCU control signals with the bits of PMMR2 can further reduce PLD AC power

teconsumption.

ole Table 31. Power Management mode registers PMMR0(1)

bsBit

Name

Description

OBit 0 X

0

Not used, and should be set to zero.

Bit 1

0=

off

APD Enable

1=

on

Automatic Power-down (APD) is disabled.

Automatic Power-down (APD) is enabled.

Bit 2 X

0

Not used, and should be set to zero.

Bit 3 PLD Turbo

0=

on

PLD Turbo mode is on

1=

off

PLD Turbo mode is off, saving power.

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Doc ID 7833 Rev 7

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