PIC32MX230F064C-I/TL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F064C-I/TL

32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX

4.2 Control Registers

Register 4-1 through Register 4-8 are used for setting

the RAM and Flash memory partitions for data and

code.

REGISTER 4-1: BMXCON: BUS MATRIX CONFIGURATION REGISTER

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0

U-0

U-0

U-0

31:24

—

—

—

U-0

U-0

U-0

23:16

—

—

—

U-0

U-0

U-0

15:8

—

—

—

U-0

R/W-1

U-0

7:0

—

BMX

WSDRM

—

U-0

—

R/W-1

BMX

ERRIXI

U-0

—

U-0

—

U-0

—

R/W-1

BMX

ERRICD

U-0

—

U-0

—

U-0

—

R/W-1

BMX

ERRDMA

U-0

—

R/W-0

U-0

—

R/W-1

BMX

ERRDS

U-0

—

R/W-0

U-0

—

R/W-1

BMX

ERRIS

U-0

—

R/W-1

BMXARB<2:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

bit 31-21 Unimplemented: Read as ‘0’

bit 20 BMXERRIXI: Enable Bus Error from IXI bit

1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus

0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus

bit 19 BMXERRICD: Enable Bus Error from ICD Debug Unit bit

1 = Enable bus error exceptions for unmapped address accesses initiated from ICD

0 = Disable bus error exceptions for unmapped address accesses initiated from ICD

bit 18 BMXERRDMA: Bus Error from DMA bit

1 = Enable bus error exceptions for unmapped address accesses initiated from DMA

0 = Disable bus error exceptions for unmapped address accesses initiated from DMA

bit 17 BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode)

1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access

0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access

bit 16 BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode)

1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access

0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access

bit 15-7 Unimplemented: Read as ‘0’

bit 6

BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit

1 = Data RAM accesses from CPU have one wait state for address setup

0 = Data RAM accesses from CPU have zero wait states for address setup

bit 5-3 Unimplemented: Read as ‘0’

bit 2-0 BMXARB<2:0>: Bus Matrix Arbitration Mode bits

111 = Reserved (using these Configuration modes will produce undefined behavior)

•

•

•

011 = Reserved (using these Configuration modes will produce undefined behavior)

010 = Arbitration Mode 2

001 = Arbitration Mode 1 (default)

000 = Arbitration Mode 0

© 2011 Microchip Technology Inc.

Preliminary

DS61168C-page 73

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