ST72F324J2TCRS View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72F324J2TCRS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

Figure 50. Generic SS timing diagram

On-chip peripherals

MOSI/MISO

Master SS

Slave SS

(if CPHA=0)

Slave SS

(if CPHA=1)

Byte 1

Byte 2

Byte 3

Figure 51. Hardware/software slave select management

t(s) SSM bit

duc SSI bit

ro SS external pin

1

SS internal

0

Obsolete Product(s) - Obsolete P Note:

Master mode operation

In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and

phase are configured by software (refer to the description of the SPICSR register).

The idle state of SCK must correspond to the polarity selected in the SPICSR register (by

pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).

How to operate the SPI in master mode

To operate the SPI in master mode, perform the following steps in order:

1. Write to the SPICR register:

– Select the clock frequency by configuring the SPR[2:0] bits.

– Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.

Figure 52 shows the four possible configurations.

Note: The slave must have the same CPOL and CPHA settings as the master.

2. Write to the SPICSR register:

– Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin

high for the complete byte transmit sequence.

3. Write to the SPICR register:

– Set the MSTR and SPE bits.

Note: MSTR and SPE bits remain set only if SS is high.

Caution: If the SPICSR register is not written first, the SPICR register setting (MSTR bit) might not be

taken into account.

The transmit sequence begins when software writes a byte in the SPIDR register.

Doc ID 13841 Rev 1

101/193

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