ST72F324J2TCRS View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72F324J2TCRS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

On-chip peripherals

SPIE

R/W

SPE

R/W

SPR2

R/W

MSTR

R/W

CPOL

R/W

CPHA

R/W

SPR[1:0]

R/W

Table 55. SPICR register description

Bit Name

Function

Serial Peripheral Interrupt Enable

This bit is set and cleared by software.

7 SPIE 0: Interrupt is inhibited.

1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or OVR = 1 in the

SPICSR register.

) Serial Peripheral Output Enable

roduct(s 6 SPE

This bit is set and cleared by software. It is also cleared by hardware when, in

master mode, SS = 0 (see Master mode fault (MODF) on page 104). The SPE bit

is cleared by reset, so the SPI peripheral is not initially connected to the external

pins.

0: I/O pins free for general purpose I/O

1: SPI I/O pin alternate functions enabled

P Divider Enable

Obsolete 5 SPR2

This bit is set and cleared by software and is cleared by reset. It is used with the

SPR[1:0] bits to set the baud rate. Refer to Table 56: SPI master mode SCK

frequency.

0: Divider by 2 enabled

1: Divider by 2 disabled

Note: This bit has no effect in slave mode.

) - Master mode

roduct(s 4 MSTR

This bit is set and cleared by software. It is also cleared by hardware when, in

master mode, SS = 0 (see Master mode fault (MODF) on page 104).

0: Slave mode

1: Master mode. The function of the SCK pin changes from an input to an output

and the functions of the MISO and MOSI pins are reversed.

P Clock Polarity

Obsolete3 CPOL

This bit is set and cleared by software. This bit determines the idle state of the

serial Clock. The CPOL bit affects both the master and slave modes.

0: SCK pin has a low level idle state

1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication byte boundaries, the SPI must be

disabled by resetting the SPE bit.

Clock Phase

2 CPHA

This bit is set and cleared by software.

0: The first clock transition is the first data capture edge.

1: The second clock transition is the first capture edge.

Note: The slave must have the same CPOL and CPHA settings as the master.

Serial clock frequency

1:0 SPR[1:0]

These bits are set and cleared by software. Used with the SPR2 bit, they select

the baud rate of the SPI serial clock SCK output by the SPI in master mode

(seeTable 56).

Note: These 2 bits have no effect in slave mode.

Doc ID 13841 Rev 1

107/193

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