ST72F324J2TCRS View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72F324J2TCRS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

On-chip peripherals

ST72324xx-Auto

Clock deviation causes

The causes which contribute to the total deviation are:

– DTRA: Deviation due to transmitter error (local oscillator error of the transmitter or

the transmitter is transmitting at a different baud rate).

– DQUANT: Error due to the baud rate quantization of the receiver.

– DREC: Deviation of the local oscillator of the receiver: This deviation can occur

during the reception of one complete SCI message assuming that the deviation

has been compensated at the beginning of the message.

– DTCL: Deviation due to the transmission line (generally due to the transceivers)

All the deviations of the system should be added and compared to the SCI clock tolerance:

DTRA + DQUANT + DREC + DTCL < 3.75%

t(s) Noise error causes

c See also the description of Noise error in Receiver on page 116.

du Start bit

ro The Noise Flag (NF) is set during start bit reception if one of the following conditions occurs:

P 1. A valid falling edge is not detected. A falling edge is considered to be valid if the three

te consecutive samples before the falling edge occurs are detected as ‘1’ and, after the

le falling edge occurs, during the sampling of the 16 samples, if one of the samples

o numbered 3, 5 or 7 is detected as a ‘1’.

bs 2. During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is

O detected as a ‘1’.

- Therefore, a valid Start bit must satisfy both the above conditions to prevent the Noise Flag

t(s) from being set.

c Data bits

u The Noise Flag (NF) is set during normal data bit reception if the following condition occurs:

rod During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the

same, the majority of the 8th, 9th and 10th samples is considered as the bit value.

te P Therefore, a valid Data bit must have samples 8, 9 and 10 at the same value to prevent the

Noise Flag from being set.

soleFigure 58. Bit sampling in Reception mode

Ob RDI line

sampled values

Sample

clock

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

7/16

6/16

7/16

One bit time

122/193

Doc ID 13841 Rev 1

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