ST72F324J2TCRS View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72F324J2TCRS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

On-chip peripherals

Table 62. SCISR register description (continued)

Bit Name

Function

Framing Error

This bit is set by hardware when a desynchronization, excessive noise or a break

character is detected. It is cleared by a software sequence (an access to the SCISR

1 FE

register followed by a read to the SCIDR register).

0: No framing error is detected

1: Framing error or break character is detected

Note: This bit does not generate interrupt as it appears at the same time as the

RDRF bit which itself generates an interrupt. If the word currently being transferred

causes both Frame Error and Overrun error, it is transferred and only the OR bit will

be set.

Parity Error

duct(s) 0 PE

This bit is set by hardware when a parity error occurs in receiver mode. It is cleared

by a software sequence (a read to the status register followed by an access to the

SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register.

0: No parity error

1: Parity error

Pro SCI Control Register 1 (SCICR1)

lete SCICR1

so 7

6

5

4

Ob R8

T8

SCID

M

) - R/W

R/W

R/W

R/W

3

WAKE

R/W

Reset value: x000 0000 (x0h)

2

1

0

PCE

PS

PIE

R/W

R/W

R/W

ct(s Table 63. SCICR1 register description

du Bit Name

Function

roReceive data bit 8

P 7 R8

This bit is used to store the 9th bit of the received word when M = 1.

te Transmit data bit 8

le6 T8

This bit is used to store the 9th bit of the transmitted word when M = 1.

so Disabled for low power consumption

Ob When this bit is set the SCI prescalers and outputs are stopped and the end of the

5 SCID current byte transfer in order to reduce power consumption.This bit is set and

cleared by software.

0: SCI enabled

1: SCI prescaler and outputs disabled

Word length

4M

This bit determines the word length. It is set or cleared by software.

0: 1 Start bit, 8 data bits, 1 Stop bit

1: 1 Start bit, 9 data bits, 1 Stop bit

Note: The M bit must not be modified during a data transfer (both transmission and

reception).

Doc ID 13841 Rev 1

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