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ST72F324K2TCR View Datasheet(PDF) - STMicroelectronics

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ST72F324K2TCR Datasheet PDF : 194 Pages
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Electrical characteristics
ST72324xx-Auto
12.10 Control pin characteristics
12.10.1 Asynchronous RESET pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Table 106. Asynchronous RESET pin
Symbol
Parameter
Conditions
Min
Typ
Max Unit
VIL
Input low level voltage(1)
0.16xVDD
VIH Input high level voltage(1)
0.85xVDD
V
Vhys Schmitt trigger voltage hysteresis(2)
) VOL Output low level voltage(3)
VDD = 5V, IIO = +2mA
2.5
0.2
0.5
t(s IIO Driving current on RESET pin
2
mA
uc RON Weak pull-up equivalent resistor VDD = 5V
20
d tw(RSTL)out Generated reset pulse duration
Internal reset sources
20
ro th(RSTL)in External reset pulse hold time(5)
2.5
te P tg(RSTL)in Filtered glitch duration(6)
30
120
kΩ
30
42(4)
µs
200
ns
le 1. Data based on characterization results, not tested in production.
o 2. Hysteresis voltage between Schmitt trigger switching levels.
bs 3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O
ports and control pins) must not exceed IVSS.
O 4. Data guaranteed by design, not tested in production.
- 5. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the
t(s) RESET pin with a duration below th(RSTL)in can be ignored.
6. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy
Obsolete Produc environments.
166/193
Doc ID 13841 Rev 1

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