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ST72F324K2TCR View Datasheet(PDF) - STMicroelectronics

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ST72F324K2TCR Datasheet PDF : 194 Pages
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Electrical characteristics
ST72324xx-Auto
Figure 82. SPI slave timing diagram with CPHA = 0(1)
SS INPUT
tsu(SS)
tc(SCK)
th(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO)
MISO OUTPUT See note 2
tw(SCKH)
tw(SCKL)
tv(SO)
MSB OUT
Bit 6 OUT
th(SO)
ttrf((SSCCKK))
LSB OUT
tdis(SO)
See
note 2
tsu(SI)
th(SI)
MOSI INPUT
MSB IN
Bit 1 IN
LSB IN
t(s) 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
c 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
u mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
d configuration.
Pro Figure 83. SPI slave timing diagram with CPHA = 1(1)
lete SS INPUT
tsu(SS)
so CPHA=1
CPOL=0
b CPHA=1
O CPOL=1
) - ta(SO)
ct(s MISO OUTPUT
see
note 2
tw(SCKH)
tw(SCKL)
HZ
tsu(SI)
tc(SCK)
tv(SO)
MSB OUT
th(SI)
Bit 6 OUT
th(SS)
th(SO)
ttrf((SSCCKK))
LSB OUT
du MOSI INPUT
MSB IN
Bit 1 IN
LSB IN
tdis(SO)
see
note 2
te Pro 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
le2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
Obso configuration.
170/193
Doc ID 13841 Rev 1

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