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ST72F324J2TCRE View Datasheet(PDF) - STMicroelectronics

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ST72F324J2TCRE Datasheet PDF : 194 Pages
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ST72324xx-Auto
8
Power saving modes
Power saving modes
8.1
Introduction
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 21): Slow, Wait (Slow
Wait), Active Halt and Halt.
After a reset the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided or multiplied by 2 (fOSC2).
Obsolete Product(s) - Obsolete Product(s) 8.2
From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
Figure 21. Power saving mode transitions
High
Run
Slow
Wait
Slow Wait
Active Halt
Halt
Low
Power consumption
Slow mode
This mode has two targets:
To reduce power consumption by decreasing the internal clock speed in the device
To adapt the internal clock frequency (fCPU) to the available supply voltage
Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select the internal slow frequency (fCPU).
In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU
and peripherals are clocked at this lower frequency (fCPU).
Note:
Slow Wait mode is activated when entering the Wait mode while the device is already in
Slow mode.
Doc ID 13841 Rev 1
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