I/O ports
ST72324xx-Auto
Table 31. I/O port interrupt control/wake-up capability
Interrupt event
Event flag Enable Control bit Exit from WAIT Exit from HALT
External interrupt on selected
external event
-
DDRx, ORx
Yes
Yes
9.5.1
I/O port implementation
The I/O port register configurations are summarized Table 32.
Table 32. Port configuration
Port Pin name
t(s) PA7:6
uc Port A PA5:4
rod PA3
P PB3
Port B
te PB4, PB2:0
le Port C PC7:0
so Port D PD5:0
b Port E PE1:0
- O PF7:6, 4
t(s) Port F PF2
PF1:0
Input (DDR = 0)
OR = 0
OR = 1
Floating
Floating
Pull-up
Floating
Floating interrupt
Floating
Floating interrupt
Floating
Pull-up interrupt
Floating
Pull-up
Floating
Pull-up
Floating
Pull-up
Floating
Pull-up
Floating
Floating interrupt
Floating
Pull-up interrupt
Output (DDR = 1)
OR = 0
OR = 1
True open-drain
Open drain
Push-pull
Open drain
Push-pull
Open drain
Push-pull
Open drain
Push-pull
Open drain
Push-pull
Open drain
Push-pull
Open drain
Push-pull
Open drain
Push-pull
Open drain
Push-pull
Open drain
Push-pull
roduc Table 33. I/O port register map and reset values
P Address (Hex.) Register label 7
6
5
4
3
2
1
0
teReset value of all I/O port registers 0
0
0
0
0
0
0
0
le 0000h
PADR
so 0001h
PADDR
MSB
LSB
Ob 0002h
PAOR
0003h
PBDR
0004h
PBDDR
MSB
LSB
0005h
PBOR
0006h
PCDR
0007h
PCDDR
MSB
LSB
0008h
PCOR
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Doc ID 13841 Rev 1