ST72F324K4TATRE View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72F324K4TATRE

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

On-chip peripherals

10 On-chip peripherals

ST72324xx-Auto

10.1 Watchdog timer (WDG)

10.1.1 Introduction

The Watchdog timer is used to detect the occurrence of a software fault, usually generated

by external interference or by unforeseen logical conditions, which causes the application

program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on

expiry of a programmed time period, unless the program refreshes the counter’s contents

before the T6 bit becomes cleared.

) 10.1.2

Obsolete Product(s) - Obsolete Product(s 10.1.3

Main features

● Programmable free-running downcounter

● Programmable reset

● Reset (if Watchdog activated) when the T6 bit reaches zero

● Optional reset on HALT instruction (configurable by option byte)

● Hardware Watchdog selectable by option byte

Functional description

The counter value stored in the Watchdog Control register (WDGCR bits T[6:0]), is

decremented every 16384 fOSC2 cycles (approx.), and the length of the timeout period can

be programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls

over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin

for typically 30µs.

The application program must write in the WDGCR register at regular intervals during

normal operation to prevent an MCU reset. This downcounter is free-running: it counts down

even if the watchdog is disabled. The value to be stored in the WDGCR register must be

between FFh and C0h:

● The WDGA bit is set (Watchdog enabled)

● The T6 bit is set to prevent generating an immediate reset

● The T[5:0] bits contain the number of increments which represents the time delay

before the Watchdog produces a reset (see Figure 31: Approximate timeout duration).

The timing varies between a minimum and a maximum value due to the unknown

status of the prescaler when writing to the WDGCR register (see Figure 32).

Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by

a reset.

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is

cleared).

If the Watchdog is activated, the HALT instruction generates a reset.

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Doc ID 13841 Rev 1

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