ST72F324K4TATRE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72F324K4TATRE
STMicroelectronics
ST72F324K4TATRE Datasheet PDF : 194 Pages
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On-chip peripherals
MCC beep control register (MCCBCR)
MCCBCR
7
6
5
4
3
Reserved
-
ST72324xx-Auto
Reset value: 0000 0000 (00h)
2
1
0
BC[1:0]
R/W
Table 41. MCCBCR register description
Bit Name
Function
7:2 - Reserved, must be kept cleared
t(s) Beep Control
duc 1:0 BC[1:0]
These 2 bits select the PF1 pin beep capability (see Table 42). The beep output
signal is available in Active Halt mode but has to be disabled to reduce the
consumption.
Pro Table 42.
te BC1
ole 0
bs 0
O 1
- 1
Beep frequency selection
BC0
Beep mode with fOSC2 = 8 MHz
0
Off
1
~2 kHz
0
~1 kHz
1
~500 Hz
Output
Beep signal
~50% duty cycle
ct(s) Table 43. Main clock controller register map and reset values
du Address
ro (Hex.)
Register label
7
6
5
4
3
2
te P 002Bh
SICSR
Reset value
AVDIE AVDF LVDRF
0
0
0
x
0
0
le 002Ch
Obso 002Dh
MCCSR
Reset value
MCCBCR
Reset value
MCO CP1 CP0 SMS TB1 TB0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
WDGRF
0
x
OIE
OIF
0
0
BC1 BC0
0
0
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Doc ID 13841 Rev 1
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