ST72F324K4TATRE View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72F324K4TATRE

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

On-chip peripherals

ST72324xx-Auto

Input capture

In this section, the index, i, may be 1 or 2 because there are two input capture functions in

the 16-bit timer.

The two 16-bit input capture registers (IC1R/IC2R) are used to latch the value of the free

running counter after a transition is detected on the ICAPi pin (see Figure 40).

Table 44. Input capture byte distribution

Register

MS byte

ICiR

ICiHR

LS byte

ICiLR

The ICiR registers are read-only registers.

t(s) The active transition is software programmable through the IEDGi bit of Control Registers

(CRi).

uc Timing resolution is one count of the free running counter: (fCPU/CC[1:0]).

rod Procedure

P To use the input capture function select the following in the CR2 register:

te ● Select the timer clock (CC[1:0]) (see Table 50).

le ● Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2

o pin must be configured as floating input or input with pull-up without interrupt if this

s configuration is available).

Ob Select the following in the CR1 register:

- ● Set the ICIE bit to generate an interrupt after an input capture coming from either the

t(s) ICAP1 pin or the ICAP2 pin

● Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the

c ICAP1pin must be configured as floating input or input with pull-up without interrupt if

du this configuration is available).

ro When an input capture occurs:

P ● ICFi bit is set.

te● The ICiR register contains the value of the free running counter on the active transition

le on the ICAPi pin (see Figure 40).

o ● A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC

bs register. Otherwise, the interrupt remains pending until both conditions become true.

O Clearing the Input Capture interrupt request (that is, clearing the ICFi bit) is done in two

steps:

1. Reading the SR register while the ICFi bit is set

2. An access (read or write) to the ICiLR register

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Doc ID 13841 Rev 1

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