NXP Semiconductors
PCA85133
Universal LCD driver for low multiplex rates
VLCD
SDAACK
SDA
SCL
SYNC
CLK
OSC
FF
VDD
VLCD
80 segment drives
PCA85133
(2)
BP0 to BP3
(open-circuit)
A0 A1 A2 SA0 VSS
LCD PANEL
(up to 5120
elements)
VDD
R ≤ tr
2Cb
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
VSS
SDAACK
SDA
SCL
SYNC
CLK
OSC
FF
VDD
VLCD
80 segment drives
PCA85133
(1)
4 backplanes
BP0 to BP3
A0 A1 A2 SA0 VSS
(1) Is master (OSC connected to VSS).
(2) Is slave (OSC connected to VDD).
Fig 20. Cascaded PCA85133 configuration
013aaa047
For display sizes that are not multiple of 320 elements, a mixed cascaded system can be
considered containing only devices like PCA85133 and PCA85132. Depending on the
application, one must take care of the software command and pin connection
compatibility.
Only one master but multiple slaves are allowed in a cascade. No external clock should be
used; the slaves get the clock from the master.
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCA85133. This synchronization is guaranteed after the power-on reset. The only time
that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments or by the definition of a multiplex drive mode when
PCA85133 with different SA0 levels are cascaded).
SYNC is organized as an input/output pin; The output selection is realized as an
open-drain driver with an internal pull-up resistor. A PCA85133 asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCA85133 to assert
SYNC. The timing relationships between the backplane waveforms and the SYNC signal
for the various drive modes of the PCA85133 are shown in Figure 21.
PCA85133_1
Product data sheet
Rev. 1 — 23 October 2009
© NXP B.V. 2009. All rights reserved.
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