TDA9106 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
TDA9106 Datasheet PDF : 30 Pages
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TDA9106
OPERATING DESCRIPTION (continued)
Figure 9 : PLL1 Block Diagram
H-LOCKCAP
13
S/G 1
VSYNCIN 33
H/HVIN 38
SYNC
PROCESSOR
TRAMEXT
LOCKDET
COMP1
E2
High
Low
* SMFE : Safety Frequency Mode Enable
Figure 10 : Details of VCO
PLL1INHIB PLL1F R0 C0
LOCK/UNLOCK
3
12 11 10
STATUS
TRAMEXT SMFE *
CHARGE
PUMP
PLL
INHIBITION
H-POS
14
PHASE
ADJUST
VCO
OSC
I2C
HPOS
Adj.
Loop
Filter
12
(1.3V < V12 < 6V)
I2C Free Running
Adjustment
I0
2
a
I0
(0.80 < a < 1.30)
4 I0
11
R0
6.4V
1.6V
RS
FLIP FLOP
9
47nF
8
10 6.4V
C0
1.6V
0 0.875T T
47nF
An other feature is the capability for MCU to force
horizontal frequency through I2C to 2xF0 or 3xF0
(for burn in mode or safety requirement).In this
case, inhibition switch is opened leaving PLL1 free
but voltage on PLL1 filter is forced to 2.66Vfor 2xF0
or 4.0V for 3xF0.
The PLL1 ensures the coincidence between the
leading edge of the synchro signal and a phase
reference obtained by comparison between the
sawtooth of the VCO and an internal DC voltage
I2C adjustable between 2.8V and 4.0V (corre-
sponding to ± 10%) (see Figure 11). This voltage
has to be filtered on Pin 14 so as to optimize jitter.
The TDA9106 also includes a Lock/Unlock identi-
fication block which senses in real time wheither
PLL1 is locked on the incoming horizontal sync
signal or not. The resulting information is available
on Hlockout (see Synchro Processor). The block
function is described in Figure 12.
The NOR1 gate is receiving the phase comparator
output pulses (which also drive the charge pump).
When PLL1 is locked, on point A there is a very
small negative pulse (about 100ns) at each hori-
20/30
zontal cycle, so after RC filter, there is a high level
on Pin 13 which forces Hlockout to low level. Hys-
terisis comparator detects locking when Pin 13 is
reaching 6.5V and unlocking when Pin 13 is de-
creasing to 6.0V.
Figure 11 : PLL1 Timing Diagram
H Osc
Sawtooth 7/8TH
1/8TH
Phase REF1
6.4V
2.8V<Vb<4.0V
Vb
1.6V
H Synchro
Phase REF1 is obtained by comparison between the sawtooth and
a DC voltage adjustable between 2.8V and 4.0V. The PLL1 en-
sures the exact coincidence between the signals phase REF and
HSYNS. A ± T/10 phase adjustment is possible.
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