CDB8952T-IQ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB8952T-IQ Datasheet PDF : 86 Pages
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CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
10BASE-T Configuration Register - Address 1Ch
15
14
13
12
11
10
9
8
Reserved
7
National
Compatibility
Mode
6
LED3 Blink
Enable
5
4
Enable LT/10 SQE Enable
3
Reserved
2
Low Rx
Squelch
1
Polarity
Disable
0
Jabber Enable
BIT
15:8
7
NAME
TYPE
Reserved
Read Only
National Compatibil- Read/Write
ity Mode
RESET
0000 0000
1
6
LED3 Blink Enable Read/Write 0
DESCRIPTION
When set, registers and bits that are not compatible
with the National DP83840 are disabled and writes to
these registers are ignored.
When set, LED3 will blink during auto-negotiation and
will indicate Link Good status upon completion of
auto-negotiation. When clear, LED3 indicates Link
Good status only.
5
Enable LT/10
Read/Write 1
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit (bit
7) is set.
When set, this bit enables the transmission of link
pulses.
When clear, link pulses are disabled and a good link
condition is forced. If link pulses are disabled during
100 Mb/s operation with auto-negotiation enabled,
the CS8952T will go into 10 Mb/s mode. If operating
in 100 Mb/s mode with no auto-negotiation, then
clearing this bit has no effect.
4
SQE Enable
Read/Write Reset to the logic When set, and if the CS8952T is in half-duplex mode,
inverse of the
this bit enables the 10BASE-T SQE function. When
value on the
the part is in repeater mode, this bit is cleared and
REPEATER pin. may not be set.
3
Reserved
Read Only 1
This bit should be read as a don’t care and, when
written, should be written to 1.
2
Low Rx Squelch Read/Write 0
When clear, the 10BASE-T receiver squelch thresh-
olds are set to levels defined by the ISO/IEC 8802-3
specification. When set, the thresholds are reduced
by approximately 6 dB. This is useful for operating
with “quiet” cables that are longer than 100 meters.
1
Polarity Disable Read/Write 0
The 10BASE-T receiver automatically determines the
polarity of the received signal at the RXD+/RXD-
input. When this bit is clear, the polarity is corrected, if
necessary. When set, no effort is made to correct the
polarity. Polarity correction will only be performed dur-
ing 10BASE-T packet reception.
DS206TPP2
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit (bit
7) is set.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
61
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